A novel FPGA architecture supporting wide, shallow memoriesOLDRIDGE, Steven W; WILTON, Steven J. E.IEEE transactions on very large scale integration (VLSI) systems. 2005, Vol 13, Num 6, pp 758-762, issn 1063-8210, 5 p.Article

High-performance software protection using reconfigurable architecturesZAMBRENO, Joseph; HONBO, Dan; CHOUDHARY, Alok et al.Proceedings of the IEEE. 2006, Vol 94, Num 2, pp 419-431, issn 0018-9219, 13 p.Article

An FPGA-Based Hardware Implementation of Configurable Pixel-Level Color Image Fusion : SPACE TECHNOLOGYBESIRIS, Dimitrios; TSAGARIS, Vassilis; FRAGOULIS, Nikolaos et al.IEEE transactions on geoscience and remote sensing. 2012, Vol 50, Num 2, pp 362-373, issn 0196-2892, 12 p.Article

An On-Demand Queue Management Architecture for a Programmable Traffic ManagerQI ZHANG; WOODS, Roger; MARSHALL, Alan et al.IEEE transactions on very large scale integration (VLSI) systems. 2012, Vol 20, Num 10, pp 1849-1862, issn 1063-8210, 14 p.Article

Low-Power Programmable FPGA Routing CircuitryANDERSON, Jason H; NAJM, Farid N.IEEE transactions on very large scale integration (VLSI) systems. 2009, Vol 17, Num 8, pp 1048-1060, issn 1063-8210, 13 p.Article

Total Power Modeling in FPGAs Under Spatial CorrelationHASSAN, Hassan A; ANIS, Mohab; ELMASRY, Mohamed et al.IEEE transactions on very large scale integration (VLSI) systems. 2009, Vol 17, Num 4, pp 578-582, issn 1063-8210, 5 p.Article

Designing a 3-D FPGA : Switch Box Architecture and Thermal IssuesGAYASEN, Aman; NARAYANAN, Vijaykrishnan; KANDEMIR, Mahmut et al.IEEE transactions on very large scale integration (VLSI) systems. 2008, Vol 16, Num 7, pp 882-893, issn 1063-8210, 12 p.Article

FPGA-based real-time optical-flow systemDIAZ, Javier; ROS, Eduardo; PELAYO, Francisco et al.IEEE transactions on circuits and systems for video technology. 2006, Vol 16, Num 2, pp 274-279, issn 1051-8215, 6 p.Article

A Dynamic Optically Reconfigurable Gate Array-Perfect EmulationSETO, Daisaku; WATANABE, Minoru.IEEE journal of quantum electronics. 2008, Vol 44, Num 5-6, pp 493-500, issn 0018-9197, 8 p.Article

Layout techniques for FPGA switch blocksSCHMIT, Herman; CHANDRA, Vikas.IEEE transactions on very large scale integration (VLSI) systems. 2005, Vol 13, Num 1, pp 96-105, issn 1063-8210, 10 p.Article

The Effect of Multi-Bit Correlation on the Design of Field-Programmable Gate Array Routing ResourcesPING CHEN, Phoebe; YE, Andy.IEEE transactions on very large scale integration (VLSI) systems. 2011, Vol 19, Num 2, pp 283-294, issn 1063-8210, 12 p.Article

A methodology for FPGA-based control implementationZHENGWEI FANG; CARLETTA, Joan E; VEILLETTE, Robert J et al.IEEE transactions on control systems technology. 2005, Vol 13, Num 6, pp 977-987, issn 1063-6536, 11 p.Article

An Efficient FPGA Design of Residue-to-Binary Converter for the Moduli Set {2n + 1, 2n, 2n - 1}GBOLAGADE, Kazeem Alagbe; VOICU, George Razvan; COTOFANA, Sorin Dan et al.IEEE transactions on very large scale integration (VLSI) systems. 2011, Vol 19, Num 8, pp 1500-1503, issn 1063-8210, 4 p.Article

Using bus-based connections to improve field-programmable gate-array density for implementing datapath circuitsYE, Andy; ROSE, Jonathan.IEEE transactions on very large scale integration (VLSI) systems. 2006, Vol 14, Num 5, pp 462-473, issn 1063-8210, 12 p.Article

Fast computation of chebyshev momentsKOTOULAS, L; ANDREADIS, I.IEEE transactions on circuits and systems for video technology. 2006, Vol 16, Num 7, pp 884-888, issn 1051-8215, 5 p.Article

A variable-radix digit-serial design methodology and its application to the discrete cosine transformLEONG, M. P; LEONG, Philip H. W.IEEE transactions on very large scale integration (VLSI) systems. 2003, Vol 11, Num 1, pp 90-104, issn 1063-8210, 15 p.Article

Routing architecture optimizations for high-density embedded programmable IP coresHALLSCHMID, Peter; WILTON, Steve J. E.IEEE transactions on very large scale integration (VLSI) systems. 2005, Vol 13, Num 11, pp 1320-1324, issn 1063-8210, 5 p.Article

A Hardware Implementation of a Run-Time Scheduler for Reconfigurable SystemsCLEMENTE, Juan Antonio; RESANO, Javier; GONZALEZ, Carlos et al.IEEE transactions on very large scale integration (VLSI) systems. 2011, Vol 19, Num 7, pp 1263-1276, issn 1063-8210, 14 p.Article

Microelectromechanical Configuration of an Optically Reconfigurable Gate Array : Optical mems and nanophotonicsMORITA, Hironobu; WATANABE, Minoru.IEEE journal of quantum electronics. 2010, Vol 46, Num 9-10, pp 1288-1294, issn 0018-9197, 7 p.Article

A Cooperative Management Scheme for Power Efficient Implementations of Real-Time Operating Systems on Soft Processors : CONFIGURABLE DESIGN-I: HIGH-LEVEL RECONFIGURATIONJINGZHAO OU; PRASANNA, Viktor K.IEEE transactions on very large scale integration (VLSI) systems. 2008, Vol 16, Num 1, pp 45-56, issn 1063-8210, 12 p.Article

Low bit rate image- compression core for onboard space applicationsCORSONELLO, Pasquale; PERRI, Stefania; STAINO, Giovanni et al.IEEE transactions on circuits and systems for video technology. 2006, Vol 16, Num 1, pp 114-128, issn 1051-8215, 15 p.Article

Adaptive delay estimation for partitioning-driven PLD placement : System-level interconnect prediction (SLIP)HUTTON, Michael; ADIBSAMII, Khosrow; LEAVER, Andrew et al.IEEE transactions on very large scale integration (VLSI) systems. 2003, Vol 11, Num 1, pp 60-63, issn 1063-8210, 4 p.Article

A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm ComputationsPAUL, Suganth; JAYAKUMAR, Nikhil; KHATRI, Sunil P et al.IEEE transactions on very large scale integration (VLSI) systems. 2009, Vol 17, Num 2, pp 269-277, issn 1063-8210, 9 p.Article

Achieving Programming Model Abstractions for Reconfigurable Computing : CONFIGURABLE DESIGN-I: HIGH-LEVEL RECONFIGURATIONANDREWS, David; SASS, Ron; ANDERSON, Erik et al.IEEE transactions on very large scale integration (VLSI) systems. 2008, Vol 16, Num 1, pp 34-44, issn 1063-8210, 11 p.Article

A low-cost parallel scalable FPGA architecture for regular and irregular LDPC decodingVERDIER, Francois; DECLERCQ, David.IEEE transactions on communications. 2006, Vol 54, Num 7, pp 1215-1223, issn 0090-6778, 9 p.Article